
f92INTERRUPT.table	EQU	$

f92_priority0		dw	STRAY.handler
f92_priority1		dw	STRAY.handler
f92_priority2		dw	STRAY.handler
f92_priority3		dw	STRAY.handler
f92_priority4		dw	FLASH.handler
f92_priority5		dw	TIMER0.handler
f92_priority6		dw	f92_TIMER1.handler
f92_priority7		dw	TIMER2.handler
f92_priority8		dw	TIMER3.handler
f92_priority9		dw	TIMER4.handler		; Unused vector.
f92_priority10		dw	TIMER5.handler		; Unused vector.
f92_priority11		dw	RTC.handler
f92_priority12		dw	UART0.handler
f92_priority13		dw	UART1.handler
f92_priority14		dw	I2C.handler
f92_priority15		dw	SPI.handler
f92_priority16		dw	PORT.A.BIT0.handler
f92_priority17		dw	PORT.A.BIT1.handler
f92_priority18		dw	PORT.A.BIT2.handler
f92_priority19		dw	PORT.A.BIT3.handler
f92_priority20		dw	PORT.A.BIT4.handler
f92_priority21		dw	PORT.A.BIT5.handler
f92_priority22		dw	PORT.A.BIT6.handler
f92_priority23		dw	PORT.A.BIT7.handler
f92_priority24		dw	PORT.B.BIT0.handler
f92_priority25		dw	PORT.B.BIT1.handler
f92_priority26		dw	PORT.B.BIT2.handler
f92_priority27		dw	PORT.B.BIT3.handler
f92_priority28		dw	PORT.B.BIT4.handler
f92_priority29		dw	PORT.B.BIT5.handler
f92_priority30		dw	PORT.B.BIT6.handler
f92_priority31		dw	PORT.B.BIT7.handler
f92_priority32		dw	PORT.C.BIT0.handler
f92_priority33		dw	PORT.C.BIT1.handler
f92_priority34		dw	PORT.C.BIT2.handler
f92_priority35		dw	PORT.C.BIT3.handler
f92_priority36		dw	PORT.C.BIT4.handler
f92_priority37		dw	PORT.C.BIT5.handler
f92_priority38		dw	PORT.C.BIT6.handler
f92_priority39		dw	PORT.C.BIT7.handler
f92_priority40		dw	PORT.D.BIT0.handler
f92_priority41		dw	PORT.D.BIT1.handler
f92_priority42		dw	PORT.D.BIT2.handler
f92_priority43		dw	PORT.D.BIT3.handler
f92_priority44		dw	PORT.D.BIT4.handler
f92_priority45		dw	PORT.D.BIT5.handler
f92_priority46		dw	PORT.D.BIT6.handler
f92_priority47		dw	PORT.D.BIT7.handler