f91INTERRUPT.table	EQU	$

priority0		dl	EMAC.RX.handler
priority1		dl	EMAC.TX..handler
priority2		dl	EMAC.SYS.handler
priority3		dl	PLL.handler
priority4		dl	FLASH.handler
priority5		dl	TIMER0.handler
priority6		dl	f91_TIMER1.handler
priority7		dl	TIMER2.handler
priority8		dl	TIMER3.handler
priority9		dl	STRAY.handler		; Unused vector.
priority10		dl	STRAY.handler		; Unused vector.
priority11		dl	RTC.handler
priority12		dl	UART0.handler
priority13		dl	UART1.handler
priority14		dl	I2C.handler
priority15		dl	SPI.handler
priority16		dl	PORT.A.BIT0.handler
priority17		dl	PORT.A.BIT1.handler
priority18		dl	PORT.A.BIT2.handler
priority19		dl	PORT.A.BIT3.handler
priority20		dl	PORT.A.BIT4.handler
priority21		dl	PORT.A.BIT5.handler
priority22		dl	PORT.A.BIT6.handler
priority23		dl	PORT.A.BIT7.handler
priority24		dl	PORT.B.BIT0.handler
priority25		dl	PORT.B.BIT1.handler
priority26		dl	PORT.B.BIT2.handler
priority27		dl	PORT.B.BIT3.handler
priority28		dl	PORT.B.BIT4.handler
priority29		dl	PORT.B.BIT5.handler
priority30		dl	PORT.B.BIT6.handler
priority31		dl	PORT.B.BIT7.handler
priority32		dl	PORT.C.BIT0.handler
priority33		dl	PORT.C.BIT1.handler
priority34		dl	PORT.C.BIT2.handler
priority35		dl	PORT.C.BIT3.handler
priority36		dl	PORT.C.BIT4.handler
priority37		dl	PORT.C.BIT5.handler
priority38		dl	PORT.C.BIT6.handler
priority39		dl	PORT.C.BIT7.handler
priority40		dl	PORT.D.BIT0.handler
priority41		dl	PORT.D.BIT1.handler
priority42		dl	PORT.D.BIT2.handler
priority43		dl	PORT.D.BIT3.handler
priority44		dl	PORT.D.BIT4.handler
priority45		dl	PORT.D.BIT5.handler
priority46		dl	PORT.D.BIT6.handler
priority47		dl	PORT.D.BIT7.handler
